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rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad630 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 balanced modulator/demodulator functional block diagram cm off adj cm off adj diff off adj diff off adj 6 3 4 5 2.5k amp a 2.5k amp b ? 10k 10k 17 5k 8 9 10 comp 19 18 1 15 7 16 14 13 11 12 r in a cha+ cha r in b chb+ chb sel b sel a 2 20 comp +v s v out r b r f r a channel status b/a ? s ad630 a b product description the ad630 is a high precision balanced modulator which com- bines a flexible commutating architecture with the accuracy and temperature stability afforded by laser wafer trimmed thin-film resistors. its signal processing applications include balanced modulation and demodulation, synchronous detection, phase detection, quadrature detection, phase sensitive detection, lock-in amplification and square wave multiplication. a network of on-board applications resistors provides precision closed loop gains of 1 and 2 with 0.05% accuracy (ad630b). these resistors may also be used to accurately configure multiplexer gains of +1, +2, +3 or +4. alternatively, external feedback may be employed allowing the designer to implement his own high gain or complex switched feedback topologies. the ad630 may be thought of as a precision op amp with two independent differential input stages and a precision comparator which is used to select the active front end. the rapid response time of this comparator coupled with the high slew rate and fast settling of the linear amplifiers minimize switching distortion. in addition, the ad630 has extremely low crosstalk between chan- nels of ?00 db @ 10 khz. the ad630 is intended for use in precision signal processing and instrumentation applications requiring wide dynamic range. when used as a synchronous demodulator in a lock-in amplifier configuration, it can recover a small signal from 100 db of inter- fering noise (see lock-in amplifier application). although optim ized for operation up to 1 khz, the circuit is useful at frequencies up to several hundred kilohertz. other features of the ad630 include pin programmable frequency compensation, optional input bias current compensation resis- tors, common-mode and differential-offset voltage adjustment, and a channel status output which indicates which of the two differential inputs is active. this device is now available to standard military drawing (desc) numbers 5962-8980701ra and 5962-89807012a. product highlights 1. the configuration of the ad630 makes it ideal for signal processing applications such as: balanced modulation and demodulation, lock-in amplification, phase detection, and square wave multiplication. 2. the application flexibility of the ad630 makes it the best choice for many applications requiring precisely fixed gain, switched gain, multiplexing, integrating-switching functions, and high-speed precision amplification. 3. the 100 db dynamic range of the ad630 exceeds that of any hybrid or ic balanced modulator/demodulator and is compa- rable to that of costly signal processing instruments. 4. the op-amp format of the ad630 ensures easy implementa- tion of high gain or complex switched feedback functions. the application resistors facilitate the implementation of most common applications with no additional parts. 5. the ad630 can be used as a two channel multiplexer with gains of +1, +2, +3, or +4. the channel separation of 100 db @ 10 khz approaches the limit which is achievable with an empty ic package. 6. the ad630 has pin-strappable frequency compensation (no external capacitor required) for stable operation at unity gain without sacrificing dynamic performance at higher gains. 7. laser trimming of comparator and amplifying channel offsets eliminates the need for external nulling in most cases. features recovers signal from +100 db noise 2 mhz channel bandwidth 45 v/ s slew rate C120 db crosstalk @ 1 khz pin programmable closed loop gains of 1 and 2 0.05% closed loop gain accuracy and match 100 v channel offset voltage (ad630bd) 350 khz full power bandwidth chips available
rev. d C2C ad630?pecifications (@ 25 c and v s = 15 v unless otherwise noted.) model ad630j/a ad630k/b ad630s min typ max min typ max min typ max unit gain open loop gain 90 110 100 120 90 110 db 1, 2 closed loop gain error 0.1 0.05 0.1 % closed loop gain match 0.1 0.05 0.1 % closed loop gain drift 2 2 2 ppm/ c channel inputs v in operational limit 1 (? s + 4 v) to (+v s ?1 v) (? s + 4 v) to (+v s ?1 v) (? s + 4 v) to (+v s ?1 v) volts input offset voltage 500 100 500 v input offset voltage t min to t max 800 160 1000 v input bias current 100 300 100 300 100 300 na input offset current 10 50 10 50 10 50 na channel separation @ 10 khz 100 100 100 db comparator v in operational limit 1 (? s + 3 v) to (+v s ?1.5 v) (? s + 3 v) to (+v s ?1.5 v) (? s + 3 v) to (+v s ?1.3 v) volts switching window 1.5 1.5 1.5 mv switching window t min to t max 2.0 2.0 2.5 mv input bias current 100 300 100 300 100 300 na response time (5 mv to +5 mv step) 200 200 200 ns channel status i sink @ v ol = ? s + 0.4 v 2 1.6 1.6 1.6 ma pull-up voltage (? s + 33 v) (? s + 33 v) (? s + 33 v) volts dynamic performance unity gain bandwidth 2 2 2 mhz slew rate 3 45 45 45 v/ s settling time to 0.1% (20 v step) 3 3 3 s operating characteristics common-mode rejection 85 105 90 110 90 110 db power supply rejection 90 110 90 110 90 110 db supply voltage range 5 16.5 5 16.5 5 16.5 volts supply current 4 5 4 5 4 5 ma output voltage, @ r l = 2 k ? t min to t max 10 10 10 volts output short circuit current 25 25 25 ma temperature ranges rated performance? package 0 70 0 70 n/a c rated performance d package ?5 +85 ?5 +85 ?5 +125 c notes 1 if one terminal of each differential channel or comparator input is kept within these limits the other terminal may be taken to the positive supply. 2 i sink @ v ol = (? s + 1) volt is typically 4 ma. 3 pin 12 open. slew rate with pins 12 and 13 shorted is typically 35 v/ s. specifications subject to change without notice.
rev. d ad630 C3C absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation . . . . . . . . . . . . . . . . . . . . 600 mw output short circuit to ground . . . . . . . . . . . . . . . indefinite storage temperature, ceramic package . . . ?5 c to +150 c storage temperature, plastic package . . . . . ?5 c to +125 c lead temperature range (soldering, 10 sec) . . . . . . . . 300 c max junction temperature . . . . . . . . . . . . . . . . . . . . . . 150 c pin configurations 20-lead dip (d-20 and n-20), 20-lead soic (r-20) 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) ad630 r in a r in b ch b+ ch b ch a ch a+ diff off adj diff off adj r b r f r a cm off adj cm off adj v s sel b sel a +v s comp v out channel status b/ a 20-contact lcc (e-20a) 20 19 1 2 3 18 14 15 16 17 4 5 6 7 8 910111213 top view (not to scale) ad630 diff off adj cm off adj cm off adj channel status b/a v s ch b+ r in b r a r f r b diff off adj ch a+ r in a ch a ch b sel b sel a +v s comp v out ordering guide model temperature ranges package description package option ad630jn 0 c to 70 c plastic dip n-20 ad630kn 0 c to 70 c plastic dip n-20 AD630AR 25 c to +85 c soic r-20 AD630AR-reel ?5 c to +85 c 13" tape and reel r-20 ad630ad ?5 c to +85 c side brazed dip d-20 ad630bd ?5 c to +85 c side brazed dip d-20 ad630sd ?5 c to +125 c side brazed dip d-20 ad630sd/883b ?5 c to +125 c side brazed dip d-20 5962-8980701ra ?5 c to +125 c side brazed dip d-20 ad630se/883b ?5 c to +125 c lcc e-20a 5962-89807012a ?5 c to +125 c lcc e-20a ad630jchips 0 c to 70 c chip ad630schips ?5 c to +125 c chip thermal characteristics jc ja 20-lead plastic dip (n) 24 c/w 61 c/w 20-lead ceramic dip (d) 35 c/w 120 c/w 20-lead leadless chip carrier (e) 35 c/w 120 c/w 20-lead soic (r-20) 38 c/w 75 c/w chip metalization and pinout dimensions shown in inches and (mm). contact factory for latest dimensions. chip availability the ad630 is available in laser trimmed, passivated chip form. the figure shows the ad630 metalization pattern, bond- ing pads and dimensions. ad630 chips are available; consult factory for details. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad630 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. d ad630 C4C rev. d 10 15 5 1 10 100 1k 10k 100k 1m resistive load c l = 100pf f = 1khz cap in 5k v o 100pf r l v i 5k output voltage v tpc 2. output voltage vs. resistive load input voltage v dv o dt v/ s 60 0 60 5 3 4 2 1 1 40 20 40 20 4 023 5 uncompensated compensated tpc 5. dv dt o vs. input voltage 10 18 5 0 5 10 15 supply voltage v output voltage v 15 5k 100pf v i 5k 2k v o f = 1khz c l = 100pf tpc 3. output voltage swing vs. supply voltage frequency hz 120 60 0 1m 100 100 80 20 40 10 1k 100k 10k uncompensated 10m 0 45 90 open loop gain db 135 180 compensated open loop phase degrees %&', -&.
/ frequency hz 15 10 5 1k 10k 1m 100k r l = 2k c l = 100pf 2k 5k 5k v i v o 100pf output voltage v tpc 1. output voltage vs. frequency frequency hz common mode rejection db 120 60 0 110 100k 100 1k 10k 100 80 40 20 tpc 4. common-mode rejection vs. frequency ad630 typical performance characteristics C4C
rev. d ad630 C5C 20mv 500ns 20mv 100 90 10 0% 20mv/div (v o ) 20mv/div (v i ) top trace: v o bottom trace: v i 5k 10k 10k v i ch a ch b 12 v o 2 20 19 18 13 9 10 14 16 15 tpc 7. channel-to-channel switch-settling characteristic 100 90 10 0% 100mv 500ns 50mv 1mv 50mv/div (v i ) 1mv/div (a) top trace: v i middle trace: settling error (a) bottom trace: v o 100mv/div (v o ) 12 ch a middle trace (a) 10k 10k v o bottom trace tektronix 7a13 10k 1k 30pf 10k v i top trace 2 20 13 14 15 tpc 8. small signal noninverting step response 100 90 10 0% 10v 10v 1mv top trace: v i middle trace: settling error (b) bottom trace: v o 5 s 10v 20khz (v i ) 1mv/div (b) 10v/div (v o ) 12 ch a 10k 10k v o bottom trace 10k v i top trace (b) middle trace 10k hp5082-2811 20 2 13 14 15 tpc 9. large signal inverting step response
rev. d ad630 C6C two ways to look at the ad630 the functional block diagram of the ad630 (see page 1) also shows the pin connections of the internal functions. an alterna tive architectural diagram is shown in figure 1. in this diagram, the individual a and b channel preamps, the switch, and the inte- grator output amplifier are combined in a single op amp. this amplifier has two differential input channels, only one of which is active at a time. 11 15 2 20 19 18 17 8 7 12 14 13 9 10 r a 5k 2.5k r f 10k 1 16 2.5k +v s r b 10k sel b sel a b/a a b v s figure 1. architectural block diagram how the ad630 works the basic mode of operation of the ad630 may be more easy to recognize as two fixed gain stages which may be inserted into the signal path under the control of a sensitive voltage comparator. when the circuit is switched between inverting and noninverting gain, it provides the basic modulation/demodulation function. the ad630 is unique in that it includes laser-wafer-trimmed thin- film feedback resistors on the monolithic chip. the configuration shown in figure 2 yields a gain of 2 and can be easily changed to 1 by shifting r b from its ground connection to the output. the comparator selects one of the two input stages to complete an operational feedback connection around the ad630. the deselected input is off and has negligible effect on the operation. a b r a 5k r f 10k v o r b 10k v i 2 20 19 18 13 15 16 14 9 10 figure 2. ad630 symmetric gain ( 2) when channel b is selected, the resistors r a and r f are con- nected for inverting feedback as shown in the inverting gain configuration diagram in figure 3. the amplifier has sufficient loop gain to minimize the loading effect of r b at the virtual ground produced by the feedback connection. when the sign of the comparator input is reversed, input b will be deselected and a will be selected. the new equivalent circuit will be the nonin- verting gain configuration shown below. in this case r a will appear across the op amp input terminals, but since the amplifier drives this difference voltage to zero, the closed loop gain is unaffected. the two closed loop gain magnitudes will be equal when r f /r a = 1 + r f /r b , which will result from making r a equal to r f r b / (r f + r b ) the parallel equivalent resistance of r f and r b . the 5 k ? and the two 10 k ? resistors on the ad630 chip can be used to make a gain of two as shown here. by paralleling the 10 k ? resistors to make r f equal 5 k ? and omitting r b the circuit can be programmed for a gain of 1 (as shown in figure 9a). these and other configurations using the on-chip resistors present the inverting inputs with a 2.5 k ? source imped- ance. the more complete ad630 diagrams show 2.5 k ? resistors available at the noninverting inputs which can be conveniently used to minimize errors resulting from input bias currents. r a 5k r f 10k r b 10k v i v o = r f r a v i figure 3. inverting gain configuration r a 5k r f 10k r b 10k v i v o = ( 1+ r f r b ) v i figure 4. noninverting gain configuration circuit description the simplified schematic of the ad630 is shown in figure 5. it has been subdivided into three major sections, the compara tor, the two input stages and the output integrator. the compara- tor consists of a front end made up of q52 and q53, a flip-flop load formed by q3 and q4, and two current steering switching cells q28, q29 and q30, q31. this structure is designed so that a differential input voltage greater than 1.5 mv in magnitude applied to the comparator inputs will completely select one the switching cells. the sign of this input voltage determine which of the two switching cells is selected. 20 11 3 4 5 6 19 2 18 13 12 sel a sel b diff off adj diff off adj cm off adj cm off adj comp q74 q44 ch b ch b+ ch a+ ch a i55 q4 q3 q28 q31 q30 q32 c122 c121 i22 i23 v s v o i73 q52 q53 +v s q65 q34 q33 q62 q35 q36 q67 q70 q25 q24 q29 10 9 8 figure 5. ad630 simplified schematic
rev. d ad630 C7C the collectors of each switching cell connect to an input trans- conductance stage. the selected cell conveys bias currents i 22 and i 23 to the input stage it contr ols, causing it to become active. the deselected cell blocks the bias to its input stage which, as a consequence, remains off. the structure of the transconductance stages is such that they present a high impedance at their input terminals and draw no bias current when deselected. the deselected input does not interfere with the operation of the selected input insuring maxi- mum channel separation. another feature of the input structure is that it enhances the slew rate of the circuit. the current output of the active stage follows a quasi-hyperbolic-sine relationship to the dif- ferential input voltage. this means that the greater the input voltage, the harder this stage will drive the output integrator, and hence, the faster the output signal will move. this feature helps insure rapid, symmetric settling when switching between inverting and noninverting closed loop configurations. the output section of the ad630 includes a current mirror- load (q24 and q25), an integrator-voltage gain stage (q32), and complementary output buffer (q44 and q74). the outputs of both transconductance stages are connected in parallel to the current mirror. since the deselected input stage produces no output current and presents a high impedance at its outputs, there is no conflict. the current mirror translates the differen- tial output current from the active input transconductance amplifier into single ended form for the output integrator. the complementary output driver then buffers the integrator output produce a low impedance output. other gain configurations many applications require switched gains other than the 1 and 2 which the self-contained applications resistors provide. the ad630 can be readily programmed with three external resistors over a wide range of positive and negative gain by selecting and r b and r f to give the noninverting gain 1 + r f /r b and subsequent r a to give the desired inverting gain. note that when the inverting magnitude equals the noninverting magnitude, the value of r a is found to be r b r f /(r b + r f ). that is, r a should equal the parallel combination of r b and r f to match positive and nega tive gain. the feedback synthesis of the ad630 may also include reactive impedance. the gain magnitudes will match at all frequencies if the a impedance is made to equal the parallel combination of the b and f impedances. essentially the same considerations apply to the a d630 as to conventional op-amp feedback circuits. virtually any function which can be realized with simple nonin- verting ? network?feedback can be used with the ad630. a common arrangement is shown in figure 6. the low fre- quency gain of this circuit is 10. the response will have a pole (? db) at a frequency f 1/(2 100 k ? c) and a zero (3 db from the high frequency asymptote) at about 10 times this frequency. the 2 k ? resistor in series with each capacitor mitigates the loading effect on circuitry driving this circuit, eliminates stabil- ity problems, and has a minor effect on the pole-zero locations. as a result of the reactive feedback, the high frequency com- ponents of the switched input signal will be transmitted at unity gain while the low frequency components will be ampli- fied. this arrangement is useful in demodulators and lock-in amplifiers. it increases the circuit dynamic range when the modulation or interference is substantially larger than the desired signal amplitude. the output signal will contain the desired signal multiplied by the low frequency gain (which may be several hundred for large feedback ratios) with the switching signal and interference superimposed at unity gain. c v s a b 10k v o 11.11k 12 v i 100k 2k c 2k 2 20 19 18 13 7 8 9 10 figure 6. ad630 with external feedback switched input impedance the noninverting mode of operation is a high input impedance configuration while the inverting mode is a low input impedance configuration. this means that the input impedance of the circuit undergoes an abrupt change as the gain is switched under control of the comparator. if gain is switched when the input signal is not zero, as it is in many practical cases, a tran- sient will be delivered to the circuitry driving the ad630. in most applications, this will require the ad630 circuit to be driven by a low impedance source which remains ?tiff at high frequencies. generally this will be a wideband buffer amplifier. frequency compensation the ad630 combines the convenience of internal frequency compensation with the flexibility of external compensation by means of an optional self-contained compensation capacitor. in gain of 2 appl ications the noise gain which must be ad dressed for stability purposes is actually 4. in this circumstance, the phase margin of the loop will be on the order of 60 without the optional compensation. this condition provides the maximum bandwidth and slew-rate for closed-loop gains of |2| and above. when the ad630 is used as a multiplexer, or in other configura- tions where one or both inputs are connected for unity gain feedback, the phase margin will be reduced to less than 20 . this may be acceptable in applications where fast slewing is a first priority, but the transient response will not be optimum. for these applications, the self-contained compensation capacitor may be added by connecting pin 12 to pin 13. this connection reduces the closed loop bandwidth somewhat, and improves the phase margin. for intermediate conditions, such as gain of 1 where loop attenuation is 2, use of the compensation should be determined by whether bandwidth or settling response must be optimized. the optional compensation should also be used when the ad630 is driving capacitive loads or whenever conservative frequency compensation is desired. offset voltage nulling the offset voltages of both input stages and the comparator have been pretrimmed so that external trimming will only be required in the most demanding applications. the offset adjust- ment of the two input channels is accomplished by means of a differential and common-mode scheme. this facilitates fine adjustment of system errors in switched gain applications. with
rev. d ad630 C8C system input tied to 0 v, and a switching or carrier waveform applied to the comparator, a low level square wave will appear at the output. the differential offset adjustment pot can be used to null the amplitude of this square wave (pins 3 and 4). the common-mode offset adjustment can be used to zero the residual dc output voltage (pins 5 and 6). these functions should be implemented using 10k trim pots with wipers connected directly to pin 8 as shown in figures 9a and 9b. channel status output the channel status output, pin 7, is an open collector output referenced to ? s which can be used to indicate which of the two input channels is active. the output will be active (pulled low) when channel a is selected. this output can also be used to supply positive feedback around the comparator. this pro duces hysteresis which serves to increase noise immunity. figure 7 shows an example of how hysteresis may be implemented. note that the feedback signal is applied to the inverting (? terminal of the comparator to achieve positive feedback. this is because the open collector channel status output inverts the output sense of the internal comparator. 1m 100k 100k 15v +5v 100 7 8 9 10 figure 7. comparator hysteresis the channel status output may be interfaced with ttl in puts as shown in figure 8. this circuit provides appropriate level shifting from the open-collector ad630 channel status output to ttl inputs. 15v +5v ttl input ad630 +15v in 914's 6.8k 22k 100k 2n2222 7 8 figure 8. channel statusttl interface applications: balanced modulator perhaps the most commonly used configuration of the ad630 is the balanced modulator. the application resistors provide pre cise symmetric gains of 1 and 2. the 1 arrangement is shown in figure 9a and the 2 arrangement is shown in figure 9b. these cases differ only in the connection of the 10 k ? feedback resistor (pin 14) and the compensation capacitor (pin 12). note the use of the 2.5 k ? bias current compensation resistors in these examples. these resistors perform the identical function in the 1 gain case. figure 10 demonstrates the performance of the ad630 when used to modulate a 100 khz square wave carrier with a 10 khz sinusoid. the result is the double sideband sup- pressed carrier waveform. these balanced modulator topologies accept two inputs, a signal (or modulation) input applied to the amplifying channels, and a reference (or carrier) input applied to the comparator. modulated output signal carrier input cm adj diff adj 2.5k amp a amp b v 10k 10k 5k 9 10 comp 1 15 7 16 14 13 12 2 20 +v s v s ad630 a b 2.5k 19 18 17 11 8 6 5 10k 4 3 10k modulation input figure 9a. ad630 configured as a gain-of-one balanced modulator modulated output signal carrier input cm adj diff adj 2.5k amp a amp b v 10k 10k 5k 9 10 comp 1 15 7 16 14 13 12 2 20 +v s v s ad630 a b 2.5k 19 18 17 11 8 6 5 10k 4 3 10k modulation input figure 9b. ad630 configured as a gain-of-two balanced modulator 10v 5v 5v 20 s modulation input carrier input output signal .
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rev. d ad630 C9C balanced demodulator the balanced modulator topology described above will also act as a balanced demodulator if a double sideband suppressed carrier waveform is applied to the signal input and the carrier signal is applied to the reference input. the output under these circum stances will be the baseband modulation signal. higher order carrier components will also be present which can be removed with a low-pass filter. other names for this function are synchronous demodulation and phase-sensitive detection. precision phase comparator the balanced modulator topologies of figures 9a and 9b can also be used as precision phase comparators. in this case, an ac waveform of a particular frequency is applied to the signal input and a waveform of the same frequency is applied to the refer- ence input. the dc level of the output (obtained by low-pass filtering) will be proportional to the signal amplitude and phase difference between the input signals. if the signal amplitude is held constant, then the output can be used as a direct indication of the phase. when these input signals are 90 out of phase, they are said to be in quadrature and the ad630 dc output will be zero. precision rectifier-absolute value if the input signal is used as its own reference in the balanced modulator topologies, the ad630 will act as a precision recti- fier. the high-frequency performance will be superior to that which can be achieved with diode feedback and op amps. there are no diode drops which the op amp must ?eap over?with the commutating amplifier. lvdt signal conditioner many transducers function by modulating an ac carrier. a linear variable differential transformer (lvdt) is a transducer of this type. the amplitude of the output signal corresponds to core displacement. figure 11 shows an accurate synchronous demodulation system which can be used to produce a dc voltage which corresponds to the lvdt core position. the inherent precision and temperature stability of the ad630 reduce demodulator drift to a second order effect. a b 10k 10k 5k 2.5k 2.5k c 100k d 1 f ad630 2 demodulator ad544 follower b phase shifter a e1000 schaevitz lvdt 2.5kh z 2v p-p sinusoidal excitation 16 1 14 17 9 10 20 19 12 13 15 figure 11. lvdt signal conditioner ac bridge bridge circuits which use dc excitation are often plagued by errors caused by thermocouple effects, 1/f noise, dc drifts in the electronics, and line noise pick-up. one way to get around these problems is to excite the bridge with an ac waveform, amplify the bridge output with an ac amplifier, and synchronously demodu late the resulting signal. the ac phase and amplitude information from the bridge is recovered as a dc signal at the output of the synchronous demodulator. the low frequency system noise, dc drifts, and demodulator noise all get mixed to the carrier fre quency and can be remo ved by means of a low-pass filter. dynamic re sponse of the bridge must be traded off against the amount of attenua tion required to adequately suppress these residual carrier components in the selection of the filter. figure 12 is an example of an ac bridge system with the ad630 used as a synchronous demodulator. the oscilloscope photo- graph shows the results of a 0.05% bridge imbalance caused by the 1 meg resistor in parallel with one leg of the bridge. the top trace represents the bridge excitation, the upper-middle trace is the amplified bridge output, the lower-middle trace is the out- put of the synchronous demodulator and the bottom trace is the filtered dc system output. this system can easily resolve a 0.5 ppm change in bridge im pedance. such a change will produce a 3.2 mv change in the low-pass filtered dc output, well above the rto drifts and noise. 1m 1k 1k 1k 1k b a b a 5k 10k 10k 2.5 k 2.5 k c d 5k 5k 5k filter 2 f 20 2 13 12 ad524 gain 1000 1 ad630 2 demodulator 1khz bridge excitation phase shifter 2 f 2 f 16 15 17 14 9 10 figure 12. ac bridge system 100 90 10 0% 5v 20v 5v 200 s 2v 0v 0v 0v 0v bridge excitation (20v/div) (a) amplified bridge output (5v/div) (b) demodulated bridge output (5v/div) (c) filter output (2v/div) (d) figure 13. ac bridge waveforms
rev. d ad630 C10C lock-in amplifier applications lock-in amplification is a technique which is used to separate a small, narrow band signal from interfering noise. the lock-in amplifiers acts as a detector and narrow band filter combined. very small signals can be detected in the presence of large amounts of uncorrelated noise when the frequency and phase of the desired signal are known. the lock-in amplifier is basically a synchronous demodulator followed by a low-pass filter. an important measure of performance in a lock-in amplifier is the dynamic range of its demodulator. the schematic diagram of a demonstration circuit which exhibits the dynamic range of an ad630 as it might be used in a lock-in amplifier is shown in figure 14. figure 15 is an oscilloscope photo showing the recovery of a signal modulated at 400 hz from a noise signal approximately 100,000 times larger; a dynamic range of 100 db. a b 10k 100r c output low pass filter a b c r 100r ad630 10k 5k 2.5k 2.5k 20 19 17 1 16 ad542 13 ad542 14 10 9 clipped band-limited white noise 100db attenuation 0.1hz modulated 400hz carrier carrier phase reference 15 figure 14. lock-in amplifier 100 90 10 0% 5v 5v 5s 5mv modulated signal (a) (unattenuated) attenuated signal plus noise (b) output figure 15. lock-in amplifier waveforms the test signal is produced by modulating a 400 hz carrier with a 0.1 hz sine wave. the signals produced, for example, by chopped radiation (ir, optical, etc.) detectors may have similar low frequency components. a sinusoidal modulation is used for clarity of illustration. this signal is produced by a circuit similar to figure 9b and is shown in the upper trace of figure 15. it is attenuated 100,000 times normalized to the output, b, of the summing amplifier. a noise signal which might represent, for example, background and detector noise in the chopped radia- tion case, is added to the modulated signal by the summing amplifier. this signal is simply band limited clipped white noise. figure 15 shows the sum of attenuated signal plus noise in the center trace. this combined signal is demodulated synchro- nously using phase information derived from the modulator, and the result is low-pass filtered using a 2-pole simple filter which also provides a gain of 100 to the output. this recovered signal is the lower trace of figure 15. the combined modulated signal and interfering noise used for this illustration is similar to the signals often requiring a lock-in amplifier for detection. the precision input performance of the ad630 provides more than 100 db of signal range and it dynamic response permits it to be used with carrier frequencies more than two orders of magnitude higher than in this example. a more sophisticated low-pass output filter will aid in rejecting wider bandwidth interference.
rev. d ad630 C11C 20-lead ceramic dip (d-20) 20 1 10 11 0.280 (7.11) 0.300 (7.62) 0.430 (10.16) 0.300 (7.62) 0.320 (8.13) 0.085 (2.16) 0.150 (3.81) 0.210 (5.33) 0.990 (25.15) 1.010 (25.65) 0.10 (2.54) 0.015 (0.38) 0.020 (0.51) 0.040 (1.01) 0.054 (1.37) 0.300 (7.62) 0.300 (7.62) 0.008 (0.20) 0.012 (0.30) 20-lead plastic dip (n-20) 20 110 11 1.070 (27.18) 0.250 (6.350) typ 0.180 (4.572) max 0.300 (7.62) typ 0.025 (0.635) 0.045 (1.143) 0.015 (0.381) 0.021 (0.533) 0.125 (3.18) min 0.100 (2.54) typ 0.033 (0.838) typ 0.310 (7.874) typ 15 0 0.008 (0.203) 0.014 (0.356) lcc (e-20a) 1 20 4 9 8 13 19 14 3 18 bottom view 0.028 (0.71) 0.022 (0.56) 45 typ 0.015 (0.38) min 0.055 (1.40) 0.045 (1.14) 0.050 (1.27) bsc 0.075 (1.91) ref 0.011 (0.28) 0.007 (0.18) r typ 0.095 (2.41) 0.075 (1.90) 0.100 (2.54) bsc 0.200 (5.08) bsc 0.150 (3.81) bsc 0.075 (1.91) ref 0.358 (9.09) 0.342 (8.69) sq 0.358 (9.09) max sq 0.100 (2.54) 0.064 (1.63) 0.088 (2.24) 0.054 (1.37) 20-lead small outline package (r-20) 0.0125 (0.32) 0.0091 (0.23) 8 0 0.0291 (0.74) 0.0098 (0.25) 45 0.0500 (1.27) 0.0157 (0.40) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 20 11 10 1 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 0.5118 (13.00) 0.4961 (12.60) outline dimensions dimensions shown in inches and (mm).
rev. d C12C location page data sheet changed from rev. c to rev. d. changes to specifications table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 changes to pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 changes to outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 c00784C0C6/01(d) printed in u.s.a. ad630 revision history

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